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ccd65 series ceramic pack electron multiplying ccd sensor introduction the ccd65 is part of the new l3vision 2 range of products from e2v technologies. this device uses a novel output amplifier circuit that is capable of operating at an equivalent output noise of less than one electron at pixel rates of over 11 mhz (corresponding to a field rate of 50 hz). this makes the sensor well suited for scientific imaging where the illumination is limited or for video applications at very low light levels. the sensor is a frame transfer device and operates in inverted mode to suppress dark current as this is now the dominant noise source (even at 50 hz field rate). the multiplication gain may be varied by adjustment of the multiplication phase amplitude r 1 2hv. the device functions by converting photons to charge in the image area during the integration time period, then transferring this charge through the image and store sections into the readout register. following transfer through the readout register, the charge is multiplied in the gain register prior to conversion to a voltage by a low noise output amplifier. variants exist to provide the following options: * optional anti-blooming * 525- or 625-line format note that e2v technologies also supply modules for operating devices at tv rates. general data active image area ......... 11.52 x 8.64 mm image section active pixels: 625-line ........... 576(h)x288(v) 525-line ........... 576(h)x244(v) image pixel size: 625-line ..............20x30 m m 525-line ............. 20x 35.5 m m number of output amplifiers .......... 1 fill factor (for non-antibloomed devices) ..... 100% additional dark reference columns ....... 15 additional overscan rows: 625-line ................. 8 525-line ................. 6 spectral range .......... 400C 1060 nm package details (nominal, see fig. 19) ceramic package 36-pin pga (non-peltier cooled) overall dimensions .......... 27x27mm number of pins .......... 36(+1 locator) inter-pin spacing ......... 2.54 + 0.15 mm opposite row spacing ....... 22.86 + 0.25 mm window material ............. glass mounting position ............. any height of active surface above base . . . 1.65 + 0.15 mm storage and operation temperature extremes min max storage temperature ( 8 c) 7 200 +100 operating temperature ( 8 c) 7 120 +75 temperature ramping ( 8 c/min) C 5 note: operation or storage in humid conditions may give rise to ice on the sensor surface on cooling, causing irreversible damage. # e2v technologies limited 2004 a1a-ccd65_series_ceramic issue 7, june 2004 411/8438 e2v technologies limited, waterhouse lane, chelmsford, essex cm1 2qu england telephone: +44 (0)1245 493493 facsimile: +44 (0)1245 492492 e-mail: enquiries@e2vtechnologies.com internet: www.e2vtechnologies.com holding company: e2v holdings limited e2v technologies inc. 4 westchester plaza, po box 1482, elmsford, ny10523-1482 usa telephone: (914) 592-6050 facsimile: (914) 592-5148 e-mail: enquiries@e2vtechnologies.us
typical performance specifications the following are specified for standard 625-line, 50 hz operating mode at typical operating voltages. parameters are given at 293 k unless specified otherwise. where parameters differ in normal and high gain modes, both are given. where parameters differ for 525- line, 60 hz operation, this figure is stated in brackets. parameter unit min typical max output amplifier responsivity (normal mode) m v/e 7 C 1.0 C multiplication register gain (see notes 1, 2 and 3) 1 C 1000 peak signal - non-antiblooming (normal mode) e 7 /pixel 100k 250k (290k) C peak signal - antiblooming (normal mode) e 7 /pixel 60k 150k (170k) C charge handling capacity of gain register e 7 /pixel C 600k C peak output voltage (normal mode) v C 0.25 (0.29) C peak output voltage (high gain mode) v C 0.6 C readout noise at 50 hz (normal mode) (see notes 4 and 5) e 7 rms C 100 C readout noise at 50 hz (high gain mode) (see note 4) e 7 rms C 5 1C dark signal at 293 k (see note 6) e 7 /pixel/s C 290 (340) 500 dark signal non-uniformity (dsnu) at 293 k (see notes 5 and 7) e 7 /pixel/s C 120 (140) C dark signal at 273 k (see note 6) e 7 /pixel/s C 40 (50) 80 dark signal non-uniformity (dsnu) at 273 k (see notes 5 and 7) e 7 /pixel/s C 16 (20) C dynamic range (see note 8) C see note 8 C excess noise factor (see note 9) C h 2C maximum parallel transfer frequency mhz C C 1 notes 1. the typical dependence of gain on r 1 2hv is shown in fig. 1. 2. the variation of gain with r 1 2hv at different temperatures is shown in fig. 1. 3. some increase of r 1 2hv may be required throughout life to maintain gain performance. adjustment of r 1 2hv should be limited to the maximum specified under operating conditions. 4. a frame rate of 50 hz corresponds to 625-line tv operation (a pixel rate of 11 mhz). 5. these noise values are dominated by reset noise in the output amplifier and it is assumed that correlated double sampling (cds) is not being employed. if cds is used to suppress the reset component, a noise of 10 e 7 can typically be achieved at a pixel rate of 1 mhz with a noise floor of 4 e 7 rms. at 11 mhz tv rate the noise with cds is about 35 e 7 and, assuming a 20 pf load, the output will be settled to 1%. these values are inferred by design and not measured. 6. for the variation of dark signal with temperature, refer to fig. 2. the dark signal has the usual temperature dependent component and an additional weakly temperature dependent component, which is independent of the integration time. 7. dsnu is defined as the 1 s variation of the dark signal. 8. dynamic range is defined as the maximum output signal divided by the total noise referenced to the input of the readout register. as gain is increased, the effective readout noise decreases with a consequential increase in dynamic range. this improvement continues until the pixel full well with applied gain exceeds the charge handling capacity of the gain register. this is illustrated in fig. 3 for an output amplifier noise of 100 e 7 . 9. the excess noise factor is defined as the factor by which the multiplication process increases the shot noise on the image when multiplication gain is used. ccd65_series_ceramic, page 2 # e2v technologies
device cosmetic performance grade 1 devices are supplied to the blemish specification shown below. note that incorrect biasing of the device may result in spurious dark or white blemishes appearing. these will be eliminated if the biases are adjusted. test conditions operating mode device run in standard 2-phase interlace tv mode (50 hz field rate for 625-line devices, 60 hz field rate for 525-line devices). sensor temperature 18 + 3 8 c. multiplication gain set to approximately 1000. illumination set to give a signal level of approximately 50 e 7 /pixel/field (roughly corresponding to quarter moonlight scene illumination through an f/1.4 lens). blemish specification black columns black defects are counted when they have a responsivity of less than 80% of the local mean signal at approximately the specified multiplication gain and level of illumination. a black column contains at least 9 contiguous black defects. white columns white defects are pixels having a dark signal generation rate corresponding to an output signal of greater than 5% of multiplication register capacity at a gain of 1000. a white column contains at least 9 contiguous white defects. pin-head columns pin-head columns are manifest as a partial dark column with a bright pixel showing photoresponse at the end of the column nearest to the readout register. pin-head columns are counted when the black column has a responsivity of less than 80% of the local mean signal at approximately the specified multiplication gain and level of illumination. a pin-head column contains at least 9 black defects. specification for grade 1 devices parameter specification white columns 0 black columns 0 pin-head columns 0 ordering information part number format operating mode anti-blooming window ccd65-06-*-a81 625-line imo shielded permanent ccd65-06-*-a82 625-line imo none temporary ccd65-05-*-a83 525-line imo shielded permanent ccd65-05-*-a84 525-line imo none temporary ccd65-05-*-b44 525-line imo none permanent ccd65-06-*-b45 625-line imo none permanent ccd65-06-*-b46 625-line imo shielded temporary ccd65-05-*-b47 525-line imo shielded temporary # e2v technologies ccd65_series_ceramic, page 3
1000 100 10 1 35 37 39 41 43 45 r 1 2hv (v) gain t= 7 4 8 c t=12 8 c t=46 8 c 8047b figure 1: typical variation of multiplication gain with r 1 2hv at different temperatures figure 2: typical variation of dark signal with temperature ccd65_series_ceramic, page 4 # e2v technologies 100 10 1 0.1 7 50 5 1015202530 package temperature ( 8 c) dark signal (e 7 /pixel/frame) 8048a
10 000 1000 100 1 10 100 1000 multiplication gain dynamic range t=0 8 c t=20 8 c 8049a figure 3: typical variation of intra-scene dynamic range with gain (non-antibloomed) assumed amplifier noise =100 e 7 rms (no cds). see note 8 for the definition of dynamic range. figure 4: typical spectral response of antibloomed and non-antibloomed devices at t = 20 8 c # e2v technologies ccd65_series_ceramic, page 5 300 250 200 150 100 50 0 400 500 600 700 800 900 1000 wavelength (nm) responsivity (ma/w) 8050 qe = 50% qe = 40% qe = 30% antibloomed non-antibloomed
100 80 60 40 20 0 0 5 10 15 20 25 30 spatial frequency f s (cycles/mm) horizontal mtf (%) 8051 850 nm 600 nm nyquist limit aliasing apparent f s =50 7 f s figure 5: typical horizontal resolution figure 6: typical vertical resolution vertical mtf shown for 625-line devices ccd65_series_ceramic, page 6 # e2v technologies 100 80 60 40 20 0 02468101214161820 spatial frequency f s (cycles/mm) vertical mtf (%) 8052 850 nm 600 nm nyquist limit aliasing apparent f s =33.3 7 f s
absolute maximum ratings maximum ratings are with respect to ss. pin connection min (v) max (v) 1ss 0 2 abd 7 0.3 +25 3r 1 2 7 20 +20 4r 1 1 7 20 +20 5r 1 3 7 20 +20 6r 1 2hv 7 20 +50 7r 1 dc 7 20 +20 8 n.c. 9dd 7 0.3 +25 10 ss 0 11 rd 7 0.3 +25 12 og 7 20 +20 13 1 r 7 20 +20 14 gd 7 0.3 +25 15 n.c. 16 n.c. 17 n.c. 18 n.c. 19 ss 0 20 dod 7 0.3 +32 21* dos 7 0.3 +25 22* os 7 0.3 +25 23 od 7 0.3 +32 24 r 1 3 7 20 +20 25 r 1 1 7 20 +20 26 r 1 2 7 20 +20 27 abg 7 20 +20 28 ss 0 29 n.c. 30 s 1 2 7 20 +20 31 s 1 1 7 20 +20 32 n.c. 33 i 1 1 7 20 +20 34 i 1 2 7 20 +20 35 n.c. 36 n.c. n.c. not connected. * permanent damage may result if, in operation, os or dos experience short circuit conditions. maximum voltages between pairs of pins: pin connection pin connection min (v) max (v) 23 od 22 os 7 15 +15 20 dod 21 dos 7 15 +15 6r 1 2hv 7 r 1 dc 7 20 +50 6r 1 2hv 24 r 1 3 7 20 +50 output transistor current (ma) 20 esd handling procedures ccd sensors, in common with most high performance ic devices, are static sensitive. in certain cases a static electricity discharge may destroy or irreversibly degrade the device. accordingly, full anti-static handling precautions should be taken whenever using a ccd sensor or module. these include: * working at a fully grounded workbench. * operator wearing a grounded wrist strap. * all receiving socket pins to be positively grounded. * unattended ccds should not be left out of their conducting foam or socket. all devices are provided with internal protection circuits to most gate electrodes but not to the other pins. evidence of incorrect handling will terminate the warranty. exposure to radiation exposure to radiation may irreversibly damage the device and result in degradation of performance. users wishing to operate the device in a radiation environment are advised to consult e2v technologies. # e2v technologies ccd65_series_ceramic, page 7
operating conditions typical operating voltages are as given in the table below. some adjustment within the minimum-maximum range specified may be required to optimise performance. connection pulse amplitude or dc level (v) min typical max i 1 1,2 high +5 (see note 10) +7 +9 (see note 10) i 1 1,2 low C 7 5C s 1 1,2 high +5 (see note 10) +7 +9 (see note 10) s 1 1,2 low C 7 5C r 1 1,2,3 high +10 +12 +13 r 1 1,2,3 low C 0 C r 1 2hv high +20 +40 +50 (see note 3) r 1 2hv low 0 +4 C 1 r high see note 11 +10 see note 11 1 r low C 0 C r 1 dc +2 +4 +5 og +1 +3 +5 abg C 0 C ss 0 +4.5 +7 od, dod +25 +28 +32 rd +15 +18 +20 abd +10 +15 +20 gd +15 +23 +25 dd +20 +24 +25 notes 10. i 1 and s 1 adjustment may be common. 11. 1 r high level may be adjusted in common with r 1 1,2,3. an external load is required. this can either be a resistor of about 2 k o (non-critical) or a constant current type of about 10 ma. the total on-chip power dissipation is in the range 300 C 400 mw, depending on the details of the voltages and clock timings used. drive pulse waveform specification the following are suggested pulse rise and fall times. clock pulse typical rise time (ns) typical fall time (ns) typical pulse overlap i 1 30 30 @90% points s 1 30 30 @90% points r 1 1 10 10 @90% points r 1 2 10 10 @90% points r 1 3 10 10 @90% points r 1 2hv 25 25 see note 13 r 1 2hv sine sine sinusoid- high on falling edge of r 1 1 notes 12. register clock pulses are as shown in the line timing diagram, fig. 11. 13. an example clocking scheme is shown in fig. 7. r 1 2hv can also be operated with a normal clock pulse, as shown in fig. 8. the requirement for successful clocking is that r 1 2hv reaches its maximum amplitude before r 1 1 goes low. ccd65_series_ceramic, page 8 # e2v technologies
r 1 2hv r 1 1 r 1 2 r 1 3 8237 figure 7: clocking scheme for multiplication gain (sine wave clocking scheme) figure 8: clocking scheme for multiplication gain (conventional clocking scheme) # e2v technologies ccd65_series_ceramic, page 9 r 1 2hv r 1 1 r 1 2 r 1 3 8054a
1 r r 1 3 t 1 t w t 2 8055 pulse timings and overlaps figure 9: reset pulse t w = 10 ns typical t 1 = output valid t 2 4 0ns figure 10: pulse and output timing ccd65_series_ceramic, page 10 # e2v technologies r 1 3 1 r os dos reset feedthrough signal output vos 8056
electrical interface characteristics electrode capacitances at mid clock levels connection capacitance to ss inter-phase capacitances total capacitance units i 1 1 10 1 11 nf i 1 2 10 1 11 nf s 1 1 7.5 1 8.5 nf s 1 2 7.5 1 8.5 nf r 1 1 45 73 118 pf r 1 2 324173pf r 1 3 67 70 137 pf r 1 2hv 35 45 80 pf series resistances connection approximate total series resistance i 1 112 o i 1 212 o s 1 114 o s 1 214 o r 1 16 o r 1 26 o r 1 36 o r 1 2hv 8 o approximate output impedance large signal amplifier 250 o # e2v technologies ccd65_series_ceramic, page 11
s 1 1 4 m s typ 607 cycles @ 11.109 mhz s 1 2 r 1 1 r 1 2 r 1 3 r 1 2hv 1 r video blanking 31 cycles 3 cycles 10 cycles 711 r 1 clock periods @ 11.109 mhz 10.5 m s nominal sample dark ref. pixels sync. 8057 figure 11: line timing diagram (625-line tv) figure 12: frame timing diagram (625-line tv) ccd65_series_ceramic, page 12 # e2v technologies i 1 1 i 1 2 s 1 1 s 1 2 r 1 1 r 1 2 r 1 3 r 1 2hv 1 r 4 2h read out first tv field h=64 m s read out second tv field 296 line transfer cycles 296 cycles @ 0.5 C 1 mhz additional 1 1 pulses 312.5h integrate second tv field integrate first tv field extended 1st pulse at start of frame transfer, 4 10 m s typically 8059a
s 1 1 4 m s typ 607 cycles @ 11.125 mhz s 1 2 r 1 1 r 1 2 r 1 3 r 1 2hv 1 r video blanking 31 cycles 3 cycles 10 cycles 711 r 1 clock periods @ 11.125 mhz 10.5 m s nominal sample dark ref. pixels sync. 8058a figure 13: line timing diagram (525-line tv) figure 14: frame timing diagram (525-line tv) # e2v technologies ccd65_series_ceramic, page 13 i 1 1 i 1 2 s 1 1 s 1 2 r 1 1 r 1 2 r 1 3 r 1 2hv 1 r 4 2h read out first tv field h = 63.9 m s read out second tv field 250 line transfer cycles 250 cycles @ 0.5 C 1 mhz additional 1 1 pulses 262.5h integrate second tv field integrate first tv field extended 1st pulse at start of frame transfer, 4 10 m s typically 8060b
store section 591 columns 250 rows ss abd r 1 2 r 1 1 r 1 3 r 1 2hv r 1 dc dd ss ss abg r 1 2 r 1 1 r 1 3 od os dos dod ss rd og 1 rgd i 1 2i 1 1s 1 1s 1 2 591 register elements 591 multiplication reg. elements image section 576 active columns +15 dark ref. 244 active rows 3 dark ref. rows 3 dark ref. rows 8125a 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16 overscan register elements 16 corner register elements figure 15: schematic chip diagram (625-line) figure 16: schematic chip diagram (525-line) ccd65_series_ceramic, page 14 # e2v technologies store section 591 columns 296 rows ss abd r 1 2 r 1 1 r 1 3 r 1 2hv r 1 dc dd ss ss abg r 1 2 r 1 1 r 1 3 od os dos dod ss rd og 1 rgd i 1 2i 1 1s 1 1s 1 2 591 register elements 591 multiplication reg. elements image section 576 active columns +15 dark ref. 288 active rows 4 dark ref. rows 4 dark ref. rows 8064a 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16 overscan register elements 16 corner register elements
16 overscan 14 dark reference 576 active outputs 8241 * * = partially shielded transition element figure 17: line output format (625-line and 525- line) note 14. there is a 1 line propagation delay between transferring a line from the store section to the standard register and reading it out through the os output amplifier. figure 18: output circuit schematic # e2v technologies ccd65_series_ceramic, page 15 og rd 1 r s 1 1 (internal connection) od substrate ss 0 v output external load os r 1 3 r 1 2 r 1 1 c n 8061
a pin 1 indicator. see note 1 image area b a protective glass window. see note 2 image plane c d e h g j 37 pins 1 f extra pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 8063 figure 19: package outline (all dimensions without limits are nominal) ref millimetres a 26.92 + 0.27 b 10.05 c 0.76 d 4.52 + 0.45 e 1.65 + 0.15 f 0.46 + 0.05 g 2.54 + 0.15 h 4.6 + 0.3 j 22.86 outline notes 1. pin 1 is identified by a spot on the upper face of the package, and the extra pin in the same corner. 2. the device is normally supplied with a fixed, plain protective window as shown. the bk7 glass window is ar coated to give a total transmission that is typically 4 86% between 450 and 1000 nm. bk7 glass has a nominal refractive index of 1.517 at 588 nm. a removable plain window, or a fixed fibre-optic input, can be fitted if required. printed in england ccd65_series_ceramic, page 16 # e2v technologies whilst e2v technologies has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences o f any use thereof and also reserves the right to change the specification of goods without notice. e2v technologies accepts no liability beyond that set out in i ts standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information cont ained herein.

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